The present invention relates generally to the transfer of data and, more particularly, to a method and apparatus for transferring data using a clockless interface.
Large data systems require the transmission of large quantities of data at high rates throughout the system. The interfaces supporting these high data rates are typically limited by a data rate that must be lower than the available clock rate unless a power consuming phase lock loop (PLL) interface is employed. Furthermore, clock distribution and clock phase maintenance is a difficult and power consuming task for such a system. A higher performance/lower power solution is highly desirable.
The PLL recovery method requires a phase lock loop in each recovery circuit, and the phase lock loops add to the power requirements of the system. The embedded clock method requires the transmission of the associated clock with the transmitted data and requires controlled skew between the transmitted data and the clock for the entire transmission path. Other methods include oversampling clock recovery techniques. The oversampling clock recovery method requires the availability of clocks that are at a higher frequency than the data they are intended to recover. The oversampling method also requires more power due to the higher speed clocks.
What is needed is a method and apparatus for transferring data that is low power, high-speed, and can operate on self-contained mobile platforms.
Further needed is a method and apparatus for using a clockless interface for transferring data and for synchronizing of the clockless data.